1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of the Related Art
Semiconductor storage devices such as DRAM are provided with sense amplifier sections, connected to memory cell arrays comprising memory cells for storing data arranged in a matrix, and to bit line pairs, for detecting data that has been read out from the memory cells and amplifying that data. In such a DRAM, one word line is selected by a row address signal and data stored in memory cells connected to the selected word line is read out onto a bit line pair. The data read onto the bit line pair is detected by the sense amplifier section and after amplification is output to a data bus via a column switch circuit.
In a semiconductor storage device of this type, for every access cycle, because the potential difference of all bit line pairs of the selected memory cell array is made maximum (maximum potential difference will be called "array drive voltage hereinafter) OV is applied to one leg of the bit line pair while the array drive voltage VDDarray is applied to the other leg of the bit line pair. In order to reduce the power consumption of the DRAM, it is desirable to keep the array drive voltage VDDarray low, but for a reliable read operation it is necessary for the a read potential difference .DELTA.V occurring in the bit line pair to have a sufficient value. Therefore, in a conventional DRAM, it is difficult to simultaneously improve the reliability of the read operation and curtail power consumption.
To solve the above described problem, a DRAM provided with preamplifiers and main amplifiers in a sense amplifier section has been developed. These preamplifiers are normally constructed of a pair of transistors that are caused to conduct between the bit line pair and the main amplifiers at an operating point close to an off state of a saturation region as a result of gates being biased to a fixed voltage, and have a function to transfer a read potential difference .DELTA.V occurring between the bit line pair to the main amplifiers.
However, even with the DRAM provided with the preamplifiers there are problems to be solved. An allowable range for the voltage to be supplied to the gates of the transistor pair constituting the preamplifiers is confined to a few tens of mV, and in order to obtain reliable operation it is necessary to maintain manufacturing quality at a high level, and this affects manufacturing costs.
Also, in the case of a conventional DRAM a time of 100 ns is necessary to carry out a so-called presense operation, which is amplification of the potential difference of the bit line pairs by preamplifiers carried out before amplification of the potential difference of the bit line pairs by the main amplifiers. The result of this is that in the most recent DRAMs having a read operation cycle of less than 50 ns a pre-sense operation requiring a time of 100 ns becomes meaningless.
Still further, in making the preamplifiers it is normally necessary to have a PMOS transistor and an NMOS transistor of different transistor type, and when such different transistor types are laid out on a wafer a space for preventing transistor latch up is wide compared to the case when the same type transistors are laid out on a wafer. This space hinders integration of the DRAM.